A semi-systolic decoder for the PDSC-73 error-correcting code

This paper presents a semi-systolic architecture for decoding cyclic linear error-correcting codes at high speed. The architecture implements a variant of Tanner's Algorithm B, modified for simpler and faster implementation. The main features of the architecture are low computational complexity, a simple, regular arrangement of cells for easy layout, short critical paths, and a high clock rate. A prototype chip has been designed to decode a 73-bit perfect difference set code. This 46OOpm x 6800pm chip should achieve 25MHz decoding in 2pm n-well CMOS. The success of the implementation illustrates the value of using technology dependent constraints and cost measures to guide the design of algorithms and architectures.